EDN

Verification IP Reuse For Complex Networking Asics

Maximizing verification IP reuse improves verification productivity. The International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design/verification productivity ...
Electronic Design

SystemVerilog: The Complete Solution

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a ...
Design-Reuse

System Verilog based Generic Verification Methodology for IPs/ASICs/SOCs: A Case Study

This document discusses Random constraint-based verification and explains how random verification can complement the directed verification for the generic designs. In our case this is demonstrated by ...
EDN

Gabe’s Commentary: Accellera and the SystemVerilog standards process

Well-meaning attempts to forget some less-than-pleasant events of the past three years are unfortunately creating more confusion and uncertainty within the EDA community. This may in fact already have ...