System-on-chip (SoC) designs are becoming more and more complex, by whatever means you measure it: power domains, gate count, packing densities, heat dissipation capacities, etc. At such high packing ...

Designed a 4-bit counter using a J-K flip-flop that has a clocked input with reset. Performed simulations of various output parameters like rise time and fall time. The design is done using cadence ...

Now that we’ve introduced a JK flip-flop, let’s look at some circuits that we can create using it as the core element, including the T and D flip-flops. In my previous column, we started to look at ...

Digital design with combinatorial gates like AND, OR, and NOT gates is relatively straightforward. In particular, when you use these gates to form combinatorial logic, the outputs only depend on the ...

Last time I talked about how to create an adder in Verilog with an eye to putting it into a Lattice iCEstick board. The adder is a combinatorial circuit and didn’t use a clock. This time, we’ll finish ...

This file type includes high-resolution graphics and schematics when applicable. Satellite-telemetry data is digitized, multiplexed, and formatted into frames at a 1-kb/s data rate typically, and ...