EDN

“Do’s and Don’ts” when considering an FPGA to structured ASIC design methodology

More and more engineers are considering structured ASICs when they are designing advanced systems, because these components offer low unit cost, low power, and high performance along with fast ...
Design-Reuse

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach

Geneva -- September 22,2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated ...
Design-Reuse

Open-Silicon Awarded Patent for Low Power ASIC Design Methodology

MILPITAS, Calif. – September 14, 2011 – Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, announced today that the United States Patent and Trademark Office has ...
EDN

ASIC-Style Design Techniques for Programmable Devices

Advances in process technology are enabling a profound increase in the number of commercial applications for field programmable gate arrays (FPGAs). Technology breakthroughs from 10-million gate ...
Yahoo Finance

Presto Engineering Group Acquires Garfield Microelectronics Ltd, Creating Europe’s Most Comprehensive ASIC Design to Production One-Stop-Shop

Custom hardware platform used for ASIC validation and test development · GlobeNewswire Inc. MEYREUIL, France, Nov. 27, 2025 (GLOBE NEWSWIRE) -- Presto Engineering Group, a global leader in ASIC supply ...
Electronic Design

Configurable Logic Solutions Wed FPGA Flexibility With ASIC Efficiency

An ASIC's or FPGA's ability to meet an application's demands comes down to a complex tradeoff between performance, density, time-to-market, and cost. Yet Leopard Logic combines FPGA flexibility with ...
Electronic Design

ASIC-Like FPGA Methodology Saves Up To $9,925,000 In NRE Costs

Not all companies have $10 million in their back pockets for the non-recurring expenses (NRE) today's ASIC design starts require. Fortunately, that kind of cash isn't necessary anymore, thanks to ...
Semiconductor Engineering

Achieving eFPGA Timing Closure In An ASIC

When we start school as young children, one of the first lessons we learn is how to share, followed quickly by not running with scissors. As Kent Orthner, Achronix’s senior director of Systems ...
Semiconductor Engineering

Unlocking Efficiency: The Power Of IP Blocks In Silicon Chip Design

The fastest, most efficient and cost-effective way to design silicon is by leveraging intellectual property (IP) blocks. This methodology reduces risk, allows a design team to focus on its own ...