EDN

Altera’s Structured ASIC design flow now ITAR-compliant for military apps

Altera Corporation has announced that the U.S. Department of State has certified that the company's HardCopy II structured ASIC design and manufacturing flow is compliant with International Trade in ...
EDN

ASIC design flow gives CPU core custom performance

The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce ...
Semiconductor Engineering

A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)

LLM-aided interface for Open Source Chip Design,” was published by researchers at University of Bristol and Rutherford Appleton Laboratory. Abstract “The growing complexity of hardware design and the ...
Design-Reuse

Cutting a fast path to semiconductors: With special synthesis and processing, algorithms turn into silicon-but keep an eye on hardware

So you have an algorithm or a compute-intensive function you want to implement in hardware. Does that mean you have to go through the traditional ASIC design flow, writing register-transfer-level VHDL ...
Design-Reuse

Global Unichip Announces First Full Service SiP Production Flow in the Fabless ASIC Industry

With almost 10 million SiP shipment, GUC SiP service leads to a fast, low cost, and low risk way to realize products with high embedded memory requirements Hsinchu, Taiwan -- April 14, 2008 –Global ...
Semiconductor Engineering

In-Design Rail Analysis Is A Beautiful Thing

As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ...